The present invention relates to the field of integrated circuits, and, more particularly, to a filter.
A clock signal is necessary for the operation of a microcontrolled device. Moreover, the clock signal must meet certain specifications concerning power supply voltage levels and frequency. For instance, the frequency of a clock signal must be in an interval between a minimum frequency and a maximum frequency. For instance, the minimum frequency may be equal to 1 MHz, and the maximum frequency may be equal to 16 MHz.
With a quartz oscillator, for example, different types of faults can be encountered. For instance, the quartz crystal can be broken or disconnected, and its amplifier can be damaged as a result of a failure or ageing, etc. As a result, the frequency of the clock signal can become too low. In some cases, the signal output from the oscillator can suddenly disappear. Conversely, the oscillator can lock onto a harmonic resonance of the quartz crystal which is beyond the intended frequency. The frequency of the clock signal can then be too high.
Consequently, there exists a need for filtering the clock signal generated by the oscillator. Such a filter is interposed between the output of the oscillator and the clock input of the microcontrolled device. A function of the oscillator is to continuously transmit a clock signal whose frequency is within a given range. This given range is known as the specification range. The function of the filter interposed between the oscillator and the clock input of the microcontrolled device must not be confused with that of a bandpass filter. The function of the bandpass filter is to allow the transmission of the harmonics of an analog signal spectrum which falls within a predetermined frequency band, and attenuate the harmonics which fall outside that band.
FIG. 1 is a schematic diagram of a filter circuit FC placed between the output of an oscillator OSC and the clock input CLK of a microcontrolled device xcexcC. The filter circuit FC receives an non-filtered clock signal, and the clock input CL receives a filtered clock signal.
FIG. 2 shows the waveform of a signal output from the oscillator OSC, i.e., the non-filtered clock signal. This signal is a periodic signal of time period T, with each period having a positive pulse and a negative pulse. A positive pulse is a voltage step to a high level, for example +5V. A negative pulse is a voltage step to a low level, for example xe2x88x925V or 0V. The value is dependent upon whether the clock signal is two-phase or single-phase. FIG. 2 illustrates a single-phase signal.
Accordingly, the output signal of the oscillator OSC is an alternating sequence of positive and negative pulses. These pulses exhibit at their starting point a rising edge or a falling edge respectively. In general, the positive and negative pulses have the same length or duration. This corresponds to a duty cycle equal to 0.5. Duty cycle is defined as the ratio between the length of the positive pulse and the time period T.
From a functional point of view, a filtering circuit includes a high-frequency filtering circuit which does not pass on positive and negative pulses shorter than a certain duration. This duration is equal to a half-period corresponding to an upper limit frequency fH. This high-frequency filtering circuit further includes a low frequency filtering circuit for generating and sending a backup pulse in the event that no positive or negative pulse is received in a given time limit equal to the half-period corresponding to a lower limit frequency fB.
To ensure that the microcontrolled device operates correctly, the lower frequency fB of the filter is slightly lower than the minimum frequency, and the upper frequency fH is slightly higher than the maximum frequency of specification range. This range also includes oscillator output signal frequencies at the limit of the specification range. For the frequency interval cited above, the limits would typically be fB=200 kHz, and fH=20 MHz.
There currently exist clock signal filtering circuits of the above type. These filtering circuits include a circuit for generating and sending, should the need arise, a backup pulse whose length is equal to the half-period corresponding to the upper frequency limit fH. However, these circuits are not fully satisfactory. In particular, the signal sent for a low frequency limitation exhibits a duty cycle far below 0.5. This can be disadvantageous in some applications.
An object of the present invention is to overcome the above described drawbacks of known filtering circuits.
The invention provides a clock signal filtering circuit having a lower limit frequency and an upper limit frequency. The clock signal filtering circuit includes a bistable flip-flop or latch having an output which delivers a filtered clock signal, and control means for controlling changes of a state of the flip-flop. First activation means activates the control means by edges of the clock signal pulses when their duration is greater than a first threshold equal to a half-period corresponding to the upper frequency limit. Second activation means activates the control means by edges of the filtered clock signal pulses delayed by a time delay equal to a half-period corresponding to the lower frequency limit.
For the first activation means, the changes of the state of the bistable flip-flop occur at substantially regular time intervals if the duty cycle of the non-filtered clock signal is equal to 0.5. For the second activation means, the changes of the state of the bistable flip-flop occur at regular intervals to the extent that the delay introduced is identical for the positive pulses and negative pulses of the filtered clock signal. Consequently, the duty cycle of the filtered clock signal is equal to 0.5 for all circumstances.